Sr. SOC Emulation Verification Engineer (Silicon Engineering)
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
SR. SOC EMULATION VERIFICATION ENGINEER (SILICON ENGINEERING)
At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to 1.5M+ users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering). In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
- Architect, create, deploy and maintain verification testbenches to apply hardware based emulation in finding pre-silicon bugs at subsystem and SoC levels
- Port ASIC and IP RTL code to prototyping and emulation platforms
- Develop all aspects of emulator implementation, emphasizing on design partitioning, synthesis, PnR, timing, and making tradeoffs between capacity and performance
- Debug and root-cause failures efficiently in a time-constrained environment. Identify emulation hardware and environment issues from silicon design issues
- Work closely with multi-disciplinary teams - RTL designers, DV folks, system architects, SW teams to bring up the SoC in emulation
- Apply knowledge in developing methodologies and strategies for automated debug and performance measurement, working closely with tool vendors as needed
- Integrate and debug external target interfaces like UART/JTAG/SPI/I2C
- Integrate 3rd party Accelerated VIPs and Fast Models into emulation platform
- Integrate 3rd party IP for post-silicon debug support and verify functional correctness
- Leverage emulation capabilities for post-silicon validation bringup and production ramp
- Develop and maintain automation/build scripts (Python, Make, JSON)
- Bachelor’s degree in electrical engineering, computer engineering or computer science
- 5+ years of experience with design verification and test bench development
PREFERRED SKILLS AND EXPERIENCE:
- Experience with emulation technologies and methods e.g. simulation acceleration, in-circuit emulation, speed bridges, virtual prototyping, hybrid methods
- Experience with hardware emulation/FPGA Platforms and tools (Veloce, Palladium, Zebu, and/or proFPGA, Protium, HAPS)
- Experience with design verification and SystemVerilog, UVM, and C/C++ verification environments
- Working knowledge of DDR, PCIe, SPI, Ethernet, UART, eMMC, I2C
- Knowledge of ARM processors and standard Bus protocols such as AXI, ACE, CHI, APB and AHB
- Experience with SystemVerilog and C++ to model RTL components and transactors
- Experience with post-silicon bring up, debug and reproducing issues on emulator
- Experience with high performance SystemC/TLM modeling for emulation acceleration (UVM acceleration, C/C++, SCEMI pipes)
- Experience with testbench acceleration (Simulation to Emulation/FPGA prototyping)
- Experience with virtual prototyping (Android/Linux benchmarking on Hybrid Emulation platforms) using HYCON/HELIUM
- Experience with emulation and FPGA prototyping performance optimizations (Synthesis/compile frequency, runtime throughput, turn-around time, time to waveforms)
COMPENSATION & BENEFITS:
SOC Emulation Verification Engineer /Senior: $160,000-$220,000/per year
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.
Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.
- To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.
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